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notes/glossary.md

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+# Glossary
+
+**Cellular automaton / CA**  
+A discrete dynamical system comprising cells having states that are updated according to a local transition rule or evolution function.
+
+**Evolution function `F`**  
+The protected local transition function applied to a cell and a bounded neighborhood to compute a next state.
+
+**Cell state**  
+The state value stored for a CA cell. In the current contemplated embodiment, each cell may be represented by a compact multi-bit state, for example a 6-bit state.
+
+**State image / image program**  
+An initial, maintained, or loaded spatial configuration of CA cell states that performs computation by evolving under `F`.
+
+**Memory-image-defined computation**  
+Computation in which the effective machine or program is encoded in a CA state image rather than in a conventional sequential instruction stream.
+
+**Persistent propagating structure**  
+A localized CA structure, such as a glider, that propagates through the lattice while preserving recognizable identity or information.
+
+**Interaction region**  
+A spatial region of a CA image configured so that incoming propagating structures interact to perform logic, routing, detection, emission, transformation, or simulation behavior.
+
+**Output region**  
+A predetermined memory region read after one or more CA update cycles to obtain computational output.
+
+**Effective hardware architecture**  
+The logical processor, accelerator, simulation engine, or computation fabric defined by a loaded CA image, as distinguished from the fixed physical update circuitry.
+
+**Pull-based update**  
+A CA update method in which each cell computes its own next state from its current state and neighboring states, thereby avoiding multi-writer conflicts.
+
+**Symmetry-preserving conflict resolution**  
+Conflict handling in which simultaneous neighbor influences are resolved by a rule that is equivariant under selected lattice rotations, reflections, or coordinate transformations.
+
+**Bias-compensated deterministic update**  
+Conflict handling in which deterministic local priority orientations vary across cells, rows, planes, tiles, or cores according to a balanced pattern so that no lattice direction is globally preferred.
+

notes/invention_disclosure.md

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+# Invention Disclosure Notes
+
+## Core Concept
+
+The invention is a programmable cellular automaton computing substrate. A fixed hardware substrate repeatedly applies a specific local evolution function `F` to cell states stored in memory. Programs are loaded as spatial CA state images. The loaded image defines the effective computational machine.
+
+In short:
+
+**The physical update hardware is fixed; the effective machine is loaded.**
+
+## Protected Technical Center
+
+The strongest protected center is the combination of:
+
+- a specific evolution function `F`;
+- compact multi-bit CA cell states, currently contemplated as 6-bit states;
+- hardware or near-memory update circuitry implementing `F`;
+- packed representation of multiple CA cores in wider memory words;
+- deterministic race-free local updates;
+- optional symmetry-preserving or bias-compensated conflict resolution;
+- memory-image-defined computation;
+- output regions, register regions, emitter regions, detector regions, and interaction regions;
+- validation, redundancy, mirroring, coordinate transformation, or CRC/integrity bits across independent cores;
+- use of persistent propagating structures such as gliders for information transport, routing, and logic.
+
+## Invention Family
+
+### Branch 1: Core Substrate
+
+Protects the cellular automaton substrate itself:
+
+- the rule `F`;
+- cell encoding;
+- neighborhood definition;
+- update circuitry;
+- packed memory representation;
+- multi-core execution;
+- integrity and redundancy mechanisms;
+- conflict resolution without nondeterministic write races.
+
+### Branch 2: Reconfigurable Architecture Images
+
+Protects loaded images that define effective hardware:
+
+- virtual processors;
+- register regions;
+- instruction-processing structures;
+- memory interfaces;
+- glider-based logic;
+- routing networks;
+- special-purpose accelerators;
+- replaceable post-deployment architectures.
+
+### Branch 3: Native Nonlinear Simulation Images
+
+Protects direct image programs that use the native CA dynamics:
+
+- particle simulation;
+- radiation transport;
+- plasma wakefield simulation;
+- field propagation;
+- collision cascades;
+- nonlinear wave computation;
+- spatial constraint solving.
+
+## Why Not Lead With A Virtual CPU
+
+A virtual CPU is useful as a proof of expressiveness or universality, but it should not be the headline. A conventional CPU is highly optimized for serial control flow, cache hierarchy, branch prediction, register renaming, pipelining, and vector operations. A CA virtual CPU may pay substantial overhead for spatial signal routing, synchronization, glider travel time, and memory access.
+
+The commercially stronger framing is that the CA substrate natively performs spatial, nonlinear, massively parallel local computation. Some image programs may define a virtual CPU, but other image programs directly implement simulation or accelerator behavior without building an ALU or instruction-fetch loop.
+
+## Candidate Novel Phrases
+
+- memory-image-defined computation;
+- state-image-defined processor architecture;
+- programmable nonlinear computing fabric;
+- reconfigurable cellular automaton computing substrate;
+- race-free pull-based cellular automaton transition function;
+- symmetry-preserving local conflict resolution;
+- bias-compensated deterministic update tiling;
+- effective hardware updated by loading a CA image;
+- fixed physical rule, mutable logical machine.
+
+## Open Technical Details To Fill
+
+1. Exact definition of `F`.
+2. Cell bit layout, including whether 6 bits are divided into core state, phase, direction, parity, or auxiliary state.
+3. Neighborhood used by `F`, such as 6 axial neighbors, 26 Moore neighbors in 3D, or another bounded neighborhood.
+4. Whether `F` is reversible, information-conserving, or merely cell-type-count preserving.
+5. Exact conserved quantities.
+6. Examples of persistent gliders or other propagating structures.
+7. Example collision rules or interaction geometries.
+8. Details of packed 64-bit layout, including ten 6-bit cores plus spare bits.
+9. Whether spare bits are used for CRC, parity, error correction, phase, tags, or metadata.
+10. Whether conflict resolution is fully symmetric, address-derived, row-derived, tile-derived, or core-derived.
+11. Example output-region read protocol.
+12. Example image program for a particle simulator.
+13. Example image program for a virtual processor.
+14. Example image program for plasma wakefield or radiation transport.
+15. Hardware architecture: ASIC, FPGA, GPU, CPU SIMD, near-memory logic, or processing-in-memory.
+